Many rechargeable, battery operated systems use common source coupled p-channel MOSFETs (PMOSs) to connect the highest available positive voltage power supply to a supply node while isolating all other power supplies, or to isolate the supply node from all power supplies. These switching elements, which are placed in series with the main current path, cannot cause an excessive voltage drop. A voltage drop of 0.1V is hardly acceptable. If a current level of 1.0 A or higher is required, the switching element must have an on-resistance (Rds,on) below 100 mΩ. Another requirement on the switching components used in battery operated portable devices is size. The components should occupy minimal area on the printed circuit board (PCB) of the device.
Each of the PMOSs of a common source coupled PMOS pair can be implemented as an individually packaged transistor using wafer level packaging (WLP) technology. WLP technology uses solder bumps placed directly on the semiconductor die to minimize wasted area in the transistor footprint normally attributed to the molded package. An integration of independently controlled transistor pairs in a common source configuration into a single device package in an economic way cannot be realized using existing WLP technology while achieving the desired low Rds,on per switch. MOSFETs with vertical current flow have been developed and have advantageous specific resistance (Rds,on×area), but these devices have common drain electrodes, as the semiconductor substrate is used as a drain contact for the individual MOSFETs. As such, these devices cannot be arranged in a common source configuration.
Therefore, a monolithically integrated PMOS transistor pair in a common source configuration is desired.